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specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage conditi on (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. d0711 sy 20091029-s00002 no.a1988-1/15 LV5768M overview the LV5768M is a 1-channel step-down switching regulator. functions ? 1 channel step-down switching regulator controller. ? frequency decrease function at pendent. ? load-independent soft start circuit. ? on/off function. ? built-in pulse-by-pulse ocp circuit. it is detect ed by using on resistance of an external mos. ? synchronous rectification ? current mode control specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage v in max 45 v allowable pin voltage v in , sw 45 v hdrv, cboot 52 v ldrv 6.0 v between cboot to sw between cboot to hdrv 6.0 v en, ilim v in +0.3 v between v in to ilim 1.0 v v dd 6.0 v ss, fb, comp,rt v dd +0.3 v allowable power dissipation pd max mounted on a specified board. * 0.9 w operating temperature topr -40 to +85 c storage temperature tstg -55 to +150 c * specified board : 114.3mm 76.1mm 1.6mm, glass epoxy board. bi-cmos lsi 1-channel step-down switching regulator orderin g numbe r : ena1988
LV5768M no.a1988-2/15 recommended operating range at ta = 25 c parameter symbol conditions ratings unit supply voltage range v in 8.5 to 42 v error amplifier input voltage v fb 0 to 1.6 v oscillatory frequency f osc 80 to 500 khz electrical characteristics at ta = 25 c, v in = 12v parameter symbol conditions ratings unit min typ max reference voltage block internal reference voltage vref incl uding offset of e/ a 0.654 0.67 0.686 v 5v power supply v dd i out = 0 to 5ma 4.7 5.2 5.7 v triangular waveform oscillator block oscillation frequency f osc rt=220k ? 110 125 140 khz frequency variation f osc dv v in = 8.5 to 42v 1 % oscillation frequency fold back detection voltage v osc fb fb voltage detection after ss ends 0.1 v oscillation frequency after fold back f osc fb 1/3f osc khz on/off circuit block ic start-up voltage v en on 2.5 3.0 3.5 v ic off voltage v en off 1.0 1.2 1.4 v soft start circuit block soft start source current i ss sc en > 3.5v 4 5 6 a soft start sink current i ss sk en < 1v, v dd = 5v 2 ma uvlo circuit block uvlo lock release voltage v uvlo 8 v uvlo hysteresis v uvlo h 0.7 v error amplifier input bias current i ea in 100 na error amplifier gain g ea 1000 1400 1800 a/v sink output current i ea osk fb = 1.0v -100 a source output current i ea osc fb = 0v 100 a current detection amplifier gain gisns 1.5 over current limiter circuit block reference current i lim 1 -10% 18.5 +10% a over current detection comparator offset voltage v lim ofs -5 +5 mv over current detection comparator common mode input range v in -0.45 v in v pwm comparator input threshold voltage (f osc =125khz) vt max duty cycle = dmax 0.9 1.0 1.1 v vt0 duty cycle = 0% 0.4 0.5 0.6 v maximum on duty dmax 85 90 95 % output block output stage on resistance (the upper side) r onh 5 output stage on resistance (the under side) r onl 5 output stage on current (the upper side) i onh 240 ma output stage on current (the under side) i onl 240 ma the whole device standby current i ccs en < 1v 10 a mean consumption current i cca en > 3.5v 3 ma continued on next page.
LV5768M no.a1988-3/15 continued from preceding page. parameter symbol conditions ratings unit min typ max security function protection function operating temperature at high temperature tsd on * design certification 170 c protection function hysteresis at high temperature tsd hys * design certification 30 c package dimensions unit : mm (typ) 3111a pin assignment sanyo : mfp14s(225mil) 1 14 7 8 8.0 0.15 (1.0) 1.0 0.35 1.7max (1.5) 0.1 4.4 0.63 6.4 pd max -- ta 0 0.47 0.2 0.4 0.6 0.8 0.9 1.0 --40 --20 40 60 20 8085 0 100 ambient temperature , ta -- c allowable power dissipation, pd max -- w specified board : 114.3 76.1 1.6mm 3 glass epoxy board. 3 4 5 6 7 8 9 10 14 13 12 11 en rt sw cboot hdrv nc v in gnd v dd ldrv LV5768M top view 1 2 fb comp ss ilim
LV5768M no.a1988-4/15 block diagram pin function pin no. pin name description 1 fb error amplifier reverse input pin. by operating t he converter, the voltage of this pin becomes 0.67v. the voltage in which the output voltage is divided by an external resistance is applied to this pin. moreover, when this pin voltage becomes 0.1v or less after a soft start ends, the oscillatory frequency becomes 1/3. 2 comp error amplifier output pin. connect a p hase compensation circuit between this pin and gnd. 3 en on/off pin. 4 rt oscillation frequency setting pin. resist ance is connected with this pin between gnd. 5 sw pin to connect with switching node. upper part nchmosfe t external a source is connected with lower side nchmosfet external a drain. 6 cboot bootstrap capacity connection pin. this pin become s a gate drive power supply of an external nchmosfet. connect a bypath capacitor between cboot and sw. 7 hdrv an external the upper mosfet gate drive pin. 8 ldrv an external the lower mosfet gate drive pin. 9 n.c. no connection 10 v dd power supply pin for an external the lower mos-fet gate drive. 11 gnd ground pin. each reference voltage is based on the voltage of the ground pin. 12 v in power supply pin. this pin is monitored by uvlo function. when the voltage of this pin becomes 8v or more by uvlo function, the ic starts and the soft start function operates. 13 ilim reference current pin for current detection. the sink current of about 18.5 a flows to this pin. when a resistance is connected between this pin and v in outside and the voltage applied to the sw pin is lower than the voltage of the terminal side of the resistance, the upper nchm osfet is off by operating the current limiter comparator. this operation is reset with respect to each pwm pulse. 14 ss pin to connect a capacitor for soft start. a capacitor for soft start is charged by using the voltage of about 5 a. this pin ends the soft start period by using the voltage of about 1.1v and the frequency fold ba ck function becomes active. 12 v in v in 13 ilim 14 ss 1 fb comp 11 gnd 8 ldrv 10 v dd + - + - + - + - 0.67v sd + + - 1.1v sd + - 0.1v ocp comp current amp err amp ffold amp dmax = 90% pwm comp shut down(sd) 1.0v 0.5v 5v 5v regulator reference voltage saw wave oscillator fosc forcec 1/3 s r q control logic v in uvlo tsd s r q en 3 5sw 7 hdrv 6 cboot 2 5v v dd uvlo + - 0.1v ss amp + - 1.2v rt 4
LV5768M no.a1988-5/15 i/o pin equivalent circuit chart pin no. equivalent circuit fb, ss 10 1 14 11 v dd fb ss gnd 1.3v 0.1v 1.1v standard voltage 0.67v comp 10 2 11 v dd comp gnd 1.6v en 12 3 11 v in en gnd rt 10 4 11 v dd rt gnd continued on next page.
LV5768M no.a1988-6/15 continued from preceding page. pin no. equivalent circuit sw, cboot, hdrv 12 7 11 v in hdrv gnd 6 cboot 5 sw ldrv 9 11 v dd ldrv gnd 10 v dd 12 v in 10 v dd 11 gnd ilim 12 13 11 v in ilim gnd
LV5768M no.a1988-7/15 boot sequence, uvlo, and tsd operation sequence of overcurrent protection uvlo 8v v in v dd ss v out hdrv-sw ldrv tsd 7.3v v dd =90% 1.1v vref 0.67v 170 c 140 c permisson of foldback v in ilim sw i out ss fb 0.67v fb=0.1v driving usually driving usually overcurrent protection oparation overcurrent protection oparation(foldback oparation) soft start start section
LV5768M ps no.a1988-8/15 sample application circuit v in =24v, v out =12v, i out =7a, fosc=100khz q1=atp201 (sanyo) q2=atp206 (sanyo) d1=dse010 d2=cms15 (60v,3a) en ss comp cboot c7=1000pf out=12v c6=1000pf hdrv sw ldrv fb v dd gnd v in ilim rt v in =24v c12=47p f cx=1nf gnd + +
LV5768M ps no.a1988-9/15 ? part selection and set 1) output voltage set output voltage (v out ) is shown the equation (1). v out = (1 + r4 r3 )vref = (1 + 22k ? 1.3k ? )0.67 (typ) [v] (1) ex) to set output voltage of 12v, set resistors as follows: r3=1.3k ? and r4=22k ? . 2) soft start set soft start capacitor (c5) is obtained by the equation (2). c5 = i ss t ss vref = 5?t ss 0.67v [f] (2) i ss : charge current value, t ss : soft start time ex) to set soft start time of 15ms (approx.), set c5=0.1f. 3) overcurrent protector set overcurrent limit setting resistor (r5) is obtained by the equation (3). r5 = rdsoni l max i i lim = rdsonil max 18.5 [ ? ] (3) i i lim: ilim current value, ilmax: the maximum value of coil current, rdson: ron between drain and source of q1 (upper nch mos fet). ron of atp201 23m ? (when vgs=4.5v at 25c) ex) to set current limit operation point to 11.3a (l oad current) where coil pe ak current value is 12a (approx.), set r5 = 15k ? . set an optimum resistor taking variation of on resistor into consideration due to temperature change and make sure to confirm it with the user's specific board. for c6, connect a capacitor of 1000pf to filter unwanted noise for the proper operation of current limiting. on resistor of fet * rdson of fet has its own temperature coefficient and the resistor becomes higher in proportion to the temperature. * to set rdson value within the range of operating temperat ure, it is advisable that the user confirm the data sheet by the fet supplier. 4) how to set oscillation frequency oscillation frequency fosc is adju stable by rt resistor as shown in the correlation chart as follows: sw frequency setting range: 80khz to 500khz 5) boot strap capacitor set for boot strap capacitor c2, use capacitor 100 times larger than ciss of power mosfet. f osc -- r t 0 50 100 150 200 250 300 100 150 50 200 250 0 500 300 350 400 450 350 400 450 500 frequency, f osc - khz resistance, r t - k
LV5768M ps no.a1988-10/15 6) phase compensation set since LV5768M adopts current mode cont rol, low esr capacitor and solid polym er capacitor such as os capacitor can be used as output capacitor with simple phase compensation. *frequency characteristics frequency characteristics of LV5768M consis t of the following transfer functions. (1) output resistor bleeder ; h r (2) voltage gain of error amplifier ; g vea current gain (trans conductance) ; g mea (3) impedance of external phase compensation part ; z c (4) current sense loop gain ; g cs (5) output smoothing impedance ; z o fig. current control loop of LV5768M closed loop gain is obtained by the equation (5) g = h r g mea z c g cs z o r5 = vref v o gmer (r c + 1 s c c ) gcs r l 1+ s c o r l (4) from the equation (4), the frequency characteristics of closed loop gain is given by pole fp1 which consists of output capacitor co and output load resistor rl, zero point fz which is given by external resistor rc and capacitor cc of phase compensation pin comp and pole fp2 which is given by output impedance z o and external phase compensation capacitor cc of error amplifier. fp1, fz, fp2 are given by the equation (5), (6) and (7). fp1 = 1 2 c o r l (5), fz = 1 2 c c r l (6), fp2 = 1 2 z ea c c (7) * calculation of phase compensation external constants r c and c c in general, the frequency where closed loop gain becomes 1 (zero cross frequency fzc) should be 1/10 of the switching frequency (or 1/5 at the highest) to stabilize the operation of switching regulator. ex) when switching frequency of LV5768M is 100khz: fzc = 100khz 10 10khz (8) since the closed loop gain becomes 1 with this frequency, the equation (7) = 1 vref v o g mea (r c + 1 s c c ) g cs r l 1+ s c o r l = 1 (9) in reality for zero cross frequenc y, in the impedance of phase compensation capacity, since capacity element 1 s c c becomes lower enough than the resistor element r c : r c ? 1 s c c (10) osc v in 1/g cs clk + - pwm comparator current sense loop slope control logic sw l comp + - c c r c c o r l r 1 r 2 v o h r vref v i v o g ver g mer error amplifier fb
LV5768M ps no.a1988-11/15 the equation (9) becomes vref v o g mea r c r l 1+2 f zc c o r l = 1 (11) from the equation, phase comp ensation external resistor r c is obtained by the following formula. however, g cs =0.67/rdson=29a/v, g mea =1400a/v. given that output is 12v and load resistor is 1.7 ? (7a load): r c = v o vref 1 g mea 1 g cs 1+2 f zc c o r l r l (12) = 12 0.67 1 1400a/v 1 29a/v 1+2 3.14 10k 1410 1.7 1.7 39k ? (13) this is the external resistor value r c obtained from this calculation (the calculation reveals that the last block where load resistor rl is inserted is 1 ? 2 f zc c o r l . therefore, there is no need for depending r l .). when point zero f z (6) and pole fp1 (5) are the same values, they can cel out each other. hence, there is only one pole frequency for the phase characteristics of closed loop gain . in other words, you can obtain characteristics in which waveform is stable because the gain frequency lowers at -20db/dec and phase only rotates by -90 degree. since (6) = (5) f z = fp1 (14) 1 2 c o r c = 1 2 c o r l c c = r l c o r c = 1.7 1410 39k = 0.062f the external constant between phase compensator pin comp and gnd is obtained as such using ideal equations. in reality, stable phase constant should be defined based on te sting under the entire temperature, load and input voltage range. on the other hand, such ideal value is used as starting point for the assessment. in the deliverable evaluation board, the above constants are used as initial value. c c and r c are defined according to conditions of transient response. if the influence of noise is significant , it is advisable to increase constant than the c c value. 7) input capacitor selection when switching of the ic occurs, ripple current flows into the input-side capacitor of dc-dc converter. like input current, the more the output current flows, the more the rippl e current into input side capacitor flows. also, the lower the input voltage is, the more the duty expands. as a re sult, the ripple current flows more. allow higher ripple current than the result of the equation. the capacitor of inpu t side should be connected ad jacent to the power ic and minimize the inductance from the pattern layout. execution value is obtained by the equation (15). irip_in = ) 1 ( d d ? i out [arms] (15) d represents duty cycle defined by v out /v in . 8) output capacitor selection if ceramic capacitor is used to output, output ripple voltage is obtained as follows since the capacitance of esr is small. vrip = v out 8 l c o f osc 2 (1- v out v in ) [v] (16) also if electrolytic capacitor is used to output, output ripp le voltage is affected by esr since the capacitance of esr is large. in this case, output ripple voltage is obtained by the following equation. vrip = v in - v out f osc v in v out r c l [v] (17) since the allowable ripple current of electrolytic capacitor is lower compared to that of ceramic capacitor, the allowable ripple current value must not be exceeded. execution value is obtained by the following equation.
LV5768M ps no.a1988-12/15 irip_out = 1 2 3 v out (v in - v out ) l f osc v in [arms] (18) it is advisable to use ceramic capacitor in combination w ith electrolytic capacitor to reject high frequency noise. the electrolytic capacitor can be low esr al uminum electrolytic capacitor or poly mer aluminum electrolytic capacitor. 9) inductor selection l1: caution is required due to the heat generation from ch oke coil caused by overload an d load short. the inductance value is determined by output ripple voltage (vrip) and the impedance of output capacitor for switching frequency. the minimum inductance is obta ined by the equation (19). l min = v in - v out f osc v in v out r c vrip [h] (19) in the above equation, esr is used in place of the impeda nce of output capacitor. the reason is, the impedance of output capacitor for switching frequency is close to r c in many cases. however with ceramic capacitor, real impedance is used instead of r c . ex)v in (max)=24v, v out =12v, vrip=100mv, r c =9m ? , f osc =100khz l min = 24v - 12v 100k 24v 12v 9m 20mv (20) 27 [h] in the actual part selection, ripple voltage is defined fi rst, then capacitor and indu ctor are selected. take the maximum value and minimum value of input voltage, output voltage and load variation into consideration. also, the ripple current of inductor is used as basis for output inductor selection in many cases. ripple current is obtained by the equation (21). irip = v in - v out f osc l d [a] (21) d represents duty cycle defined by v out /v in . the important term is the ripple current represented as irip/i out . as long as the ripple element is less than 50%, it should not be a problem. if the ripple element is higher, inductor loss becomes significant. ex)v in =24v, v out =12v, f osc =100khz, l=45 h irip = 24v - 12v 100k 45 0.5 (22) = 1.3 [a] 10) power consumption of high side mosfet the power consumption in the external high side mosfet is represented by conduction loss and switching loss. the conduction loss of mosfet is obtained by the following equation (23). psat = i o 2 r ds(on) d [w] (23) since r ds(on) is affected by temperature, it is advisable to confirm the actual fet temp erature and data sheet. the switching loss of high side mosfet is obtained by the following equation (24). psw = v in i o t sw f sw [w] (24) i o : dc output current t sw : rise time of switching waveform f sw : switching frequency
LV5768M ps no.a1988-13/15 the junction temperature of high side mosfet is obtained by the following equation (25). tj = ta + (psat + psw) ja [w] (25) ja: package heat resistor tj should not exceed the tjmax as stated in the data sheet. 11) power consumption of low side mosfet the power consumption in low side mosfet consists of conduction loss from r ds (on) as well as from body diode and reverse recovery loss. the conduction loss due to r ds (on) is obtainable by the equation (23) which is represented in the equation (26). psat = i o 2 r ds(on) (1-d) [w] (26) the conduction loss from body diode occurs when the body diode is conducted forwardly between high side off and low side off zone, which is represented in the equation (27). pdf = 2 i o vf tdelay f sw [w] (27) vf: forward voltage of body diode tdelay: delay time immediately before surge of sw node the total power consumption of low side mosfet is obtained by the equation (28). pls = psat + pdf [w] (28) 12) power consumption of LV5768M the total power consumption of LV5768M is represented in the equation (29) given that the same mosfet is selected for high side and low side. pd_ic = (2 qg f sw + i cc a) v in [w] (29) i cc a: ic consumption current when switching is stopped.
LV5768M ps no.a1988-14/15 ? caution for pattern layout c1: input capacitor when the ic performs switching, ripple current flows into the input capacitor of dc-d c converter. the capacitor of input should be connected ad jacent to the power ic and mi nimize the inductance from patte rn layout. c1 should be connected adjacently to v in pin of the ic and q1 (high side fet- drain). if implementation to ic side is not feasible, insert adjacently to q1. c7 (bypass capacitor connected to v in pin of the ic) should be connected adjacently to v in pin and gnd pin. in rare cases, intensive ringing may occur in the v in pin by connecting bypass capacitor. the recommendation value is 1000pf. q1, q2 (d1): external fet both high and low sides are driven by nch-mosfet. in q1, a transition of sw node takes place between v in and gnd by turn on and off, where high frequency noise occurs. the noise affects the surrounding pattern layouts and parts. the high/ low side gate and sw node should be laid out as fat and short as possible without connecting all the way to hdrv, ldrv and sw pins of the ic. hdrv, ldrv and sw pins should be shielded with gnd to prevent influence from noise. when high side fet is turned on, current path is as follows: v in + (c1) --> inductor (l) --> v out (load) --> pgnd --> gnd. when low side fet is turned on, current path is as follows: inductor (l) --> v out (load) --> pgnd. by minimizing the area of current path and keeping the pattern layout fat and short, noise is eliminated and error operation is prevented. hence, q1, q2, d1, c1 and c9 should be implemented nearby. r5,c6: ilim (overcurrent limiter set pin) ilim pin detects overcurrent which is used as set point wher e current limit comparator in th e ic starts operation. the overcurrent limiter is adjustable by the resistor between i lim pin and v in pin. when the voltage of sw pin becomes lower than that of i lim pin, current limit comparator functions and turns off the high side mosfet. this operation is reset at every pwm pulse. to filter unwanted noise, c6 should be connected in parallel to the set resistor (the recommendation is 1000pf). r5 and c6 should be implemented adjacently to the v in side of the ic. if they are apart from the v in side, detection precision for overcurrent point may be deteriorated. small signal system: part for fb, comp, en, cboot, v dd and ss pins. the parts should be implemented adjacently to the ic and be connected as short as possi ble. also the gnd of the parts should have common gnd pattern as the ic. fb pattern layout should not be under nor nearby the inductor or sw node. this must be complied to avoid error operation.
LV5768M ps no.a1988-15/15 this catalog provides information as of december, 2011. specifications and inform ation herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliab ility pr oducts, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these pr obab ilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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